1. Technical Field
The present invention relates generally to the data processing field and, more particularly, to a method, system and computer program product for protecting the integrity of data transferred between an input/output bus of a data processing system and an external network.
2. Description of Related Art
During the past ten years, LAN (Local Area Network) technology, particularly Ethernet technology, has improved media speed by a factor of ten every three to four years. In contrast, during the same period, CPU (Central Processing Unit) speed has only doubled every two years or so. As a result, CPUs are becoming a bottleneck in high input/output performance systems.
In order to alleviate the additional CPU workload resulting from improvements in media speed, an increasing number of native host functions are being offloaded to the input/output (I/O) adapter. These offloaded functions have, however, created data integrity issues. For cost reasons, it is not customary for adapter vendors to provide adequate error checking for memory elements such as on-chip FIFOs, external memory and other temporary storage.
TCP/IP (Transmission Control Protocol/Internet Protocol) standards enhance data integrity with a “checksum” requirement. This checksum can be implemented in either the host or in adapter logic. When TCP/IP checksum is implemented in the adapter logic, care must be taken to ensure that bad data is detected by the TCP/IP checksum. This can be assured only when all the data paths are error protected along the entire data paths.
With PCI-Express (Peripheral Component Interconnect) bus architecture, the I/O bus protocol has improved data integrity protection with the Cyclic Redundancy Check (CRC) technique for PCI-Express based I/O links. FIG. 4 is a block diagram that schematically illustrates an Ethernet adapter system incorporated in a data processing system having a PCI-Express bus architecture that is known in the art to assist in explaining the present invention. The adapter system is generally designated by reference number 400 and couples an I/O bus 402 of a data processing system to an external network 406 in order to transfer data between memory 404 of the data processing system and network 406.
As shown in FIG. 4, on the transmit path for transferring data from I/O bus 402 to network 406, CRC checker 412 is provided on the interface between I/O bus 402 and adapter 430 that is defined by I/O link 414 specified by PCI-Express architecture. CRC checker 412 checks the CRC value for a data packet crossing I/O bus 402 from memory 404. The data packet is transferred from I/O bus 402 to network 406 through Tx packet buffer 416 and Tx MAC (Media Access Control) 418 on adapter 430, and then to network 406.
Prior to being transferred across the adapter/network interface to network 406, CRC generator 420 on adapter 430 generates a CRC value for the data packet being transferred to network 406.
On the receive path for transferring data from network 406 to I/O bus 402, CRC checker 422 on adapter 430 checks the CRC value for a data packet crossing the adapter/network interface from network 406. The received data is transferred through Rx MAC 424 and Rx packet buffer 426 on adapter 430 to I/O link 414 on the interface between adapter 430 and I/O bus 402. CRC generator 428 on I/O link 414 generates a CRC value for the data packet being transferred across I/O link 414 to I/O bus 402.
Ethernet adapter system 400 only generates and checks the CRC value at the physical layer, and data integrity is protected only on the physical medium in the network. Accordingly, although parity is implemented on the PCI-Express and the adapter's internal memory, the error checking is not as strong as would be provided in an end-to-end CRC implementation because parity does not detect double bit errors or errors associated with addressability.
It would, accordingly, be desirable to provide for end-to-end data integrity protection for data transferred between an input/output bus and an external network in a data processing system.